The present invention relates to a semiconductor device, and more particularly to an MOSFET (namely, a metal-oxide-semiconductor field effect transistor) which is formed on a semiconductor substrate and is high in operation speed and reliability, and in which the gate length in the direction from the source to the drain can be reduced below 1 .mu.m, e.g. into the submicron range.
FIG. la shows an ordinary N-channel MOSFET in which a channel is formed in the surface of a semiconductor substrate. Referring to FIG. 1a, a gate insulating film 2 is formed on a P-type semiconductor substrate 1, and a gate electrode 3 is formed on the gate insulating film 2. Further, an N.sup.+ -source region 4 and an N.sup.+ -drain region 5 are formed in the substrate 1. The operation mechanism of this MOSFET will be briefly explained. FIG. 1b is an energy band diagram in the channel portion of the MOSFET of FIG. 1a in an OFF-state thereof, and FIG. 1c is an energy band diagram in the channel portion of the above MOSFET in an ON-state. In FIGS. 1b and 1c, reference symbol E.sub.c designates the bottom of conduction band, E.sub.i a mid-gap level or the Fermi level for an intrinsic semiconductor, E.sub.F a Fermi level, E.sub.v the top of valence band, and V.sub.G a voltage applied to the gate electrode. The flat band voltage is assumed to be zero as seen from FIG. 1b. A channel, through which a drain current flows, is formed only in that surface portion of the semiconductor substrate 1 which lies beneath the gate insulating film 2. Accordingly, the drain current concentrates in a surface portion having a depth of tens of angstroms. As can be seen from FIG. 1c, a strong electric field in a y-direction (that is, a direction perpendicular to the drain current) is formed in the vicinity of the surface of the semiconductor substrate, and becomes maximum at the substrate surface. Near the surface, the electron mobility is reduced by the surface scattering effect. Thus, the conventional MOSFET of FIG. 1a encounters with the first problem that a reduction in electron mobility due to the strong electric field in the y-direction makes it impossible to obtain a large drain current.
Further, the above MOSFET encounters second problem that the characteristics of the MOSFET are deteriorated by hot carriers. When the length (in the source-drain direction) of the gate electrode is made small, the peak intensity of an electric field concentrating to that end portion of the drain region 5 which exists under the gate electrode 3, becomes large, and part of the high-energy carriers (namely, hot carriers) generated at the above end portion enter into the gate insulating film 2. Thus, the characteristics of the MOSFET are deteriorated.
In more detail, when the hot carriers enter into the gate insulating film 2, there arise various phenomena such as an increase in threshold voltage, the formation of trapping level in an interface between the semiconductor substrate and the gate insulating film, a reduction in carrier mobility, and an increase in subthreshold current. Thus, the characteristics of the MOSFET are deteriorated, and the reliability thereof is reduced. Accordingly, in order to make the gate length small, it is necessary to devise means for decreasing the peak intensity of electric field at the above end portion of the drain region.
As one of means for solving the above problems, a structure shown in FIG. 2 has been proposed in Japanese Kokai Patent Publication No. 60-50960 (1985). SUMMARY OF THE INVENTION
Now, the structure and operation mechanism of an N-channel MOSFET disclosed in the above publication will be briefly explained, by way of example.
Referring to FIG. 2, a P-type layer 7 opposite in conductivity type to the source and drain regions 4 and 5, is formed in a surface portion of a channel formation region which lies beneath the gate insulating film 2, and an N-type layer 6 of the same conductivity type but smaller in impurity concentration than the source and drain regions is formed in the remaining portion of the channel formation region, that is, beneath the P-type layer 7. The bottom of the N-type layer 6 is kept in contact with the P-type semiconductor substrate 1. FIGS. 3a and 3b are diagrams for explaining the operation of the MOSFET of FIG. 2. That is, FIG. 3a shows the energy band structure and the spread of the depletion layer (that is, hatched area) in the OFF-state of the MOSFET, and FIG. 3b shows the energy band structure and the spread of the depletion layer in the ON-state of the MOSFET. In the ON-state, as shown in FIG. 3b, each of the depletion layers is contracted, and a channel through which a current can flow, is formed in the N-type layer 6. As a result, the injection of hot carriers into a gate region is decreased, and the carrier mobility is increased. However, the above structure encounters with a problem that when the gate length is made less than 1.3 .mu.m, an MOSFET having the above structure cannot show normal operation characteristics. This problem will be explained below in more detail.
A failure in normal operation caused by making the gate length small is called "short channel effect". In order to make it possible to shorten the gate length without producing the short channel effect, it is necessary to know the current control mechanism of the MOSFET.
First, explanation will be made of the current interrupting mechanism in the MOSFET of FIG. 2. FIG. 4 shows depletion layers in the OFF-state of the MOSFET of FIG. 2 and lines of electric force in the depletion layers. It is to be noted that the OFF-state of FIG. 4 is obtained when a drain-source voltage and a gate-source voltage are made equal to 5 V and 0 V, respectively. Further, in FIG. 4, a region bounded by a pair of broken lines indicates a depletion layer, and arrows indicate lines of electric force. As shown in FIG. 4, a depletion layer due to a PN junction 9 is extended into the N-type layer 6, and another depletion layer due to another PN junction 10 between the P-type semiconductor substrate 1 and the N-type layer 6 is also extended into the N-type layer 6. These depletion layers overlap each other in the N-type layer 6, and thus a current path in the N-type layer 6 is blocked.
The depletion layers due to the PN junctions 9 and 10 are difficult to extend toward the N-type layer 6, in the vicinity of the boundary between the N-type layer 6 and each of the source and drain regions 4 and 5. This is because electrons flow from the source and drain regions 4 and 5 which are higher in impurity concentration than the N-type layer 6, into the N-type layer 6 so that a thermal equilibrium state is established, and thus portions of the N-type layer 6 existing near the source and drain regions become higher in electron density than a central portion of the N-type layer 6. The absence of a depletion layer in the neighborhood of the boundary between the N-type layer 6 and each of the source and drain regions 4 and 5 makes the length of the current blocking region formed in the N-type layer 6 smaller than the length of the N-type layer 6. Accordingly, in an MOSFET which has the OFF-state shown in FIG. 4, the effective channel length L.sub.oe is shorter than the actual length of the gate electrode 3. As a result, when the gate length of an MOSFET having the structure of FIG. 2 is made small, the short channel effect will become remarkable. That is, there arise problems such as a reduction in controllability of gate threshold voltage, a reduction in the breakdown voltage between the source region and the drain region, and the deterioration of sub-threshold characteristics.
FIG. 5 shows the potential distribution in the MOSFET having the structure of FIG. 2 which distribution is obtained by simulation. In FIG. 5, a range indicated by arrows is a region where the gate electrode 3 is provided, and the gate length is equal to 1.0 .mu.m. Further, the potential distribution of FIG. 5 is formed when the same drain-source voltage and gate-source voltage as in the OFF-state of FIG. 4 are used. Now, let us pay attention to an upper one of equipotential curves of 0.2 V, by way of example. The length of an area bounded by the above equipotential curve in a direction from the source region toward the drain region becomes small at the bottom (indicated by a dotted broken line) of the N-type layer 6. This is because the potential distribution in the layer 6 is greatly affected not only by a gate voltage but also a drain voltage. In other words, the above fact indicates that the controllabilty of the drain current by the gate voltage is decreased.
As mentioned above, the structure of FIG. 2 has some drawbacks. Further, when the above structure is actually fabricated, the short channel effect will become more serious.
FIGS. 6a to 6e show the actual structure of the MOSFET of FIG. 2, and the impurity concentration profile, the energy band structure and the spread of depletion layer in the MOSFET, in a case where the MOSFET is made by a well-known fabrication process. As shown in FIGS. 6a to 6c, a donor impurity is allowed to diffuse from the highly-doped source and drain regions 4 and 5 into the N-type layer 6 in lateral directions. While the PN junction 9 at the side surface of the P-type layer 7 is scarcely affected by such impurity diffusion because of the high impurity concentration in the P-type region 7, the impurity concentration of the lightly-doped N-type layer 6 is greatly influenced (increased) in the vicinity of the source and drain regions 4 and 5. Accordingly, in the OFF-state of the above MOSFET, the extension of depletion layer at end portions of the N-type layer 6 is suppressed to be far less than that at a central portion of the N-type layer 6, as shown in FIG. 6d and 6e. That is, it is very difficult to further reduce the gate length of an MOSFET having the structure of FIG. 2 without deteriorating the characteristics. Thus, the appearance of an MOSFET which is large in carrier mobility, is scarcely degraded by hot carrier, and moreover is small in gate length, has been strongly desired.
It is an object of the present invention to provide a semiconductor device in which a reduction in carrier mobility caused by surface scattering is made as small as possible, a strong current driving force is obtained, a current path is formed in a deep portion of a semiconductor substrate to prevent a reduction in reliability due to hot carrier, and the gate length can be made small without producing any adverse effect.
In order to attain the above object, according to the present invention, there is provided a semiconductor device having a channel formation region formed beneath a gate insulating film and between a source and a drain region, and made up of first and second semiconductor layers opposite in conductivity type to each other, in which the first semiconductor layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second semiconductor layer lies beneath the first semiconductor layer and has the same conductivity type as the source and drain regions, and the length of the second semiconductor layer between the source region and the drain region is greater than the length of the first semiconductor layer between the source region and the drain region, to avert the short channel effect.